1. Field of the Invention
The present invention relates to a power supply circuit, and more particularly to a power supply circuit that drives an inductance load.
2. Description of the Related Art
FIG. 6 is a circuit diagram showing an example of the circuit configuration of a conventional power supply circuit and a digital amplifier connected thereto.
In FIG. 6, reference numeral 51 designates a transformer, reference numerals 52 and 53 designate rectifier devices (diodes), and reference numerals 54 and 55 designate smoothing capacitors. These component parts form a capacitor-input positive and negative power supply circuit. The transformer 51 has a winding of which one end is connected to the anode of the diode 52 and the other end is connected to the cathode of the diode 53. The cathode of the diode 52 is connected to one end of the smoothing capacitor 54 and a positive voltage (+V) input terminal of the digital amplifier. The other end of the smoothing capacitor 54 is connected to a ground terminal G of the digital amplifier, a center tap of the winding of the transformer 51, and one end of the smoothing capacitor 55. The anode of the diode 53 is connected to the other end of the smoothing capacitor 55 and a negative voltage (−V) input terminal of the digital amplifier.
In the digital amplifier, symbols SW1 and SW2 designate switching transistors, such as MOSFET's, driven by an output from a PWM (Pulse Width Modulation) circuit, not shown. Symbols D1 and D2 designate diodes (flywheel diodes) connected in parallel with the switching transistors SW1 and SW2, respectively. Symbols LF, CF, and RL designates an inductor (coil), a capacitor, and a load (speaker), respectively. The positive voltage (+V) input terminal of the digital amplifier is connected to the cathode of the diode D1 and one end of the switching transistor SW1, while the negative voltage (−V) input terminal of the same is connected to the anode of the diode D2 and one end of the switching transistor SW2. The anode of the diode D1, the cathode of the diode D2, and the respective other ends of the switching transistors SW1 and SW2 are connected to one end of the inductor LF, and the other end of the inductor LF is grounded via the capacitor CF and connected to one end of the load RL. The other end of the load RL is grounded as well as connected to the ground terminal of the digital amplifier.
In the circuit configured as above, signals formed by PWM of an input signal drive the switching transistors SW1 and SW2 complementarily to drive the load RL (speaker), via a low-pass filter formed by the inductor LF and the capacitor CF. More specifically, when the switching transistor SW1 conducts (and the switching transistor SW2 does not conduct), an electric current (I+) flows from the positive power supply, as shown in FIG. 6, and then when the switching transistor SW2 conducts (and the switching transistor SW1 does not conduct), an electric current (I−) flows to the negative power supply, as shown in FIG. 6, whereby the load RL is driven. This kind of digital amplifier is known as a very highly efficient amplifier.
However, when the inductance load is driven by the positive and negative power supply circuit as described above, there is a problem of pumping operation. Hereafter, the pumping operation will be explained with reference to FIG. 7.
FIG. 7 is a timing chart showing waveforms of voltages and electric currents detected at relevant elements when a positive DC voltage VRL is supplied to the load RL.
As shown in (a) of FIG. 7, when the positive DC voltage VRL is applied to the load, a time period T1 over which the switching transistor SW1 conducts is set to be longer than a time period T2 over which the switching transistor SW2 conducts. During the time period T1 from a time point t1 to a time point t2, over which the switching transistor SW1 conducts, an electric current I1 flows from the positive power supply through a path comprised of the switching transistor SW1, the inductor LF, the load RL, and the ground ((c) of FIG. 7). Then, at the time point t2, the switching transistor SW1 is brought out of conduction and the switching transistor SW2 is brought into conduction. Even at this time, due to the inductance which has the property of maintaining the flow of the electric current, the flow of electric current is continued by an electric current I2, as illustrated in FIG. 6, which flows through a path comprised of the diode D2, the inductor LF, the load RL, and the capacitor 55 ((d) of FIG. 7). The clock of PWM has such a high frequency that before an electric current I− starts to flow to the negative power supply through the switching transistor SW2, a time point t3 is reached at which the switching transistor SW1 is brought into conduction, and the switching transistor SW2 is brought out of conduction, whereby the electric current I1 flows again. Thus, a load current IL flows through the load RL as shown in (b) of FIG. 7.
The direction in which the electric current I2 flows during the time period T2 over which the switching transistor SW2 is in conduction is opposite to the direction in which the electric current I− flows through the switching transistor SW2 during conduction thereof, so that the capacitor 55 is charged. For this reason, a voltage V2 charged in the capacitor 55 becomes higher than a voltage V1 across the capacitor 54 of the positive power supply side (V2>V1).
When a negative DC voltage is applied to the load, the power supply circuit and the digital amplifier operate in the opposite manner to that described above, and therefore the voltage V1 charged in the capacitor 54 of the positive power supply side becomes higher than the voltage V2 across the capacitor 55 of the negative power supply side (V1>V2).
As described above, the pumping operation causes imbalance in voltage between the positive power supply and the negative power supply, which results in degradation of operating efficiency. Further, since the capacitor 54 or 55 is charged with a very large amount of electric charge, it is necessary to use a capacitor with high breakdown voltage for prevention of breakage thereof.
When a bridge circuit formed of four switching elements is used to drive the load RL, the pumping operation does not occur. In this case, however, an increased number of switching transistors capable of driving a low impedance load are needed, which brings about the problem of increased cost.
A technique for preventing imbalance in voltage between the positive power supply and the negative power supply caused by the pumping operation of the positive and negative power supply circuit has already been proposed (see U.S. Pat. No. 6,169,681B1). However, the proposed technique is related to a choke-input power supply circuit, but not to the capacitor-input power supply circuit as shown in FIG. 6. Further, the circuit configuration for implementing the technique is very complicated.